Flash memories may be configured as NOR flash memories or as NAND flash memories. In a NOR flash memory, the memory cells are connected to the bit lines in parallel so that if any memory cell is turned on by the corresponding wordline, the bit line goes low. In a NAND flash memory, a number of transistors are connected in series so that a NAND flash memory structure may provide a higher density of memory cells than may be provided in a NOR flash memory. Moreover, NAND flash memories may provide faster programming and erasing times than may be provided by NOR flash memories.
Read operations for NAND flash memories are discussed, for example, in European Patent Publication No. EP 1619588 A1 to Bennett (the Bennett publication). In particular, an address may be received from a CPU and held in a requested address register. The address of a current access being made to NAND flash may be held in a current address register. The page address in the address received from the CPU may be read and compared with the current page that is being accessed from the NAND flash memory. If the requested page is not the same at the current page, then a decision is made to generate a random read to the NAND flash memory by providing the requested page address. The page address in the current address register is updated to reflect the new requested page address. The byte address in the current register is updated to read byte zero (or the first byte in the segment of the page which is being addressed when the NAND flash memory is being operated in different read modes). The read operation described above is then completed and data for the addressed page is placed in the data register to be read out byte-by-byte under control of RE pulses. As each byte is read out, the byte address is updated in the current register.